Hardware Designing and Verification of Three-Phase to Sequence Decomposer

The objective of this project is to develop a hardware model of 3-Phase to sequence converter. It will be useful in relaying circuits for faster action on any faults. The model will be implemented on a FPGA board using Verilog HDL. The input analog signal is first converted into digital signal by using ADC (Analog to Digital Converter) which can be done using the inbuilt ADC on FPGA board. A digital circuit is implemented which takes the 3-phase discrete signals as input and gives the discrete values of Positive, Negative and Zero sequence components. Finally, the sequence values can be used for the identification of the unbalanced and balanced faults (L-G, L-L, L-L-G and L-L-L) and sends the control signals to respective relays.

Developed a frequency adaptive hardware model of 3-phase to sequence decomposer for faster action on an electrical fault in the power system using FPGA boards and Verilog HDL. Got the work done published in the form of a research paper in IEEE journal.